Recessed channel access transistor device and fabrication method thereof

ABSTRACT

A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices. Moreparticularly, the present invention relates to a recessed channel accesstransistor (RCAT) device for high-density dynamic random access memory(DRAM) applications.

2. Description of the Prior Art

As the size of semiconductor devices shrinks, the gate channel lengthdecreases correspondingly, and short channel effect (SCE) and junctionleakage current become very serious problems. Recessed channel accesstransistor devices (or RCAT devices in short) have been developed tosuppressing the short channel effect by physically increasing the gatechannel length without an increase in a lateral area of a gateelectrode.

Typically, an RCAT transistor has a gate oxide layer formed on sidewallsand the bottom surface of a recess etched into a substrate, where aconductive substance fills the recess. Contrary to a planar gate typetransistor having a gate electrode formed on a planar surface of asubstrate, the RCAT transistor has a U-shaped channel along the surfaceof the recess. Therefore, the integration of the recessed-gatetransistor can be increased.

However, in a conventional RCAT device, when a drain voltage (Vd) isapplied to a capacitor that is electrically connected to an NMOStransistor, agate induced drain leakage (GIDL) problem may occur. TheGIDL adversely affects the refresh or data retention characteristic ofthe DRAM device.

SUMMARY OF THE INVENTION

It is therefore one objective of the present invention to provide animproved recessed channel access transistor device to solve theabove-mentioned prior art problems or shortcomings.

According to one embodiment of the invention, a recessed channel accesstransistor device is provided. A semiconductor substrate having thereona trench is provided. The trench extends from a main surface of thesemiconductor substrate to a predetermined depth. A buried gateelectrode is disposed at a lower portion of the trench. Agate oxidelayer is formed between the buried gate electrode and the semiconductorsubstrate. A drain doping region on a first side (cell side) of thetrench in the semiconductor substrate and a source doping region on asecond side (digit side) of the trench are formed. The source dopingregion has a junction depth that is deeper than that of the drain dopingregion. An L-shaped channel is defined along a sidewall surface on thefirst side and along a bottom surface of the trench between the draindoping region and the source doping region.

According to one aspect of the invention, a method for fabricating arecessed channel access transistor device is provided. A semiconductorsubstrate having thereon a trench extending from a main surface of thesemiconductor substrate to a predetermined depth is prepared. A gateoxide layer is formed on interior surface of the trench. A buried gateelectrode is formed at a lower portion of the trench. The capping theburied gate electrode is capped with a dielectric layer. A pad layer andhard mask layer are formed on the main surface of the semiconductorsubstrate. A recess through the pad layer and hard mask layer and intothe semiconductor substrate is formed on one side of the trench, whereina portion of the dielectric layer is revealed within the recess. Thehard mask layer is then removed. Thereafter, an ion implantation processis performed to implant dopants on both sides of the trench, therebyforming a source doping region and a drain doping region in thesemiconductor substrate. The source doping region has a junction depththat is deeper than that of the drain doping region.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the embodiments, and are incorporated in and constituteapart of this specification. The drawings illustrate some of theembodiments and, together with the description, serve to explain theirprinciples. In the drawings:

FIGS. 1-7 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a recessed channel access transistor (RCAT)device in accordance with one embodiment of the present invention;

FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a RCAT device in accordance with anotherembodiment of the present invention; and

FIGS. 11-13 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a RCAT device in accordance with yet anotherembodiment of the present invention.

It should be noted that all the figures are diagrammatic. Relativedimensions and proportions of parts of the drawings have been shownexaggerated or reduced in size, for the sake of clarity and conveniencein the drawings. The same reference signs are generally used to refer tocorresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific examples in which the embodiments may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice them, and it is to beunderstood that other embodiments may be utilized and that structural,logical and electrical changes may be made without departing from thedescribed embodiments. The following detailed description is, therefore,not to be taken in a limiting sense, and the included embodiments aredefined by the appended claims.

With regard to the fabrication of transistors and integrated circuits,the term “major surface” refers to that surface of the semiconductorlayer in and about which a plurality of transistors are fabricated,e.g., in a planar process. As used herein, the term “vertical” meanssubstantially orthogonal with respect to the major surface. Typically,the major surface is along a <100> plane of a monocrystalline siliconlayer on which the field-effect transistor devices are fabricated.

FIGS. 1-7 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a recessed channel access transistor (RCAT)device in accordance with one embodiment of the present invention. Asshown in FIG. 1, a semiconductor substrate 10 is provided. Thesemiconductor substrate 10 may be a silicon substrate, silicongermanium, gallium arsenic or other semiconductor materials. Forexample, the semiconductor substrate 10 may be a P type siliconsubstrate. A trench 12 is formed in the semiconductor substrate 10. Thetrench 12 has a depth d from the main surface 10 a of the semiconductorsubstrate 10. The trench 12 may have a substantially vertical sidewallsurface 12 a and a bottom surface 12 b connected to the sidewall surface12 a.

As shown in FIG. 2, an oxidation process may be performed to form a gateoxide layer 14 on the interior surface of the trench 12. A gateelectrode layer 16 is then deposited on the gate oxide layer 14 andfills the trench 12. The gate electrode layer 16 may comprisepolysilicon, for example.

As shown in FIG. 3, an etch back process may be performed to recess thegate electrode layer 16 such that the top surface of the recessed gateelectrode layer 16 is lower than the main surface 10 a of thesemiconductor substrate 10. Subsequently, a dielectric layer 18 such asa silicon oxide layer is deposited over the semiconductor substrate 10in a blanket manner. The dielectric layer 18 fills the trench 12,thereby forming a buried gate electrode 16 a at the lower portion of thetrench 12.

As shown in FIG. 4, a planarization process such as a chemicalmechanical polishing (CMP) process is carried out to remove excessdielectric layer 18 from the main surface 10 a of the semiconductorsubstrate 10 . At this point, the polished top surface of the dielectriclayer 18 is substantially flush with the main surface 10 a.

As shown in FIG. 5, a pad layer 22 such as a silicon oxide layer is thendeposited in a blanket manner. The pad layer 22 may be a silicon oxidelayer. A hard mask layer 24 such as a silicon nitride layer is thendeposited on the pad layer 22.

As shown in FIG. 6, a lithographic process and a dry etching process areperformed to from a recess 30 in the semiconductor substrate 10 on onesingle side of the trench 12. At this point, a portion of the dielectriclayer 18 is revealed within the recess 30. Within the recess 30, a lowertop surface 10 b of the semiconductor substrate 10 is formed.

As shown in FIG. 7, the hard mask layer 24 is stripped off, whileleaving the pad layer 22 substantially intact. Subsequently, an ionimplantation process 40 is performed to implant dopants such as N typedopants into the semiconductor substrate 10 on both sides of the trench12, that is, the digit side and the cell side in this embodiment,thereby forming a RCAT device 1 with asymmetric drain doping region 42and source doping region 44.

Due to the recess 30 on the cell side of the RCAT device 1, the PNjunction depth 44 a of the source doping region 44 on the digit side canbe formed deeper than the PN junction depth 42 a of the drain dopingregion 42 on the cell side. An L-shaped channel 50 maybe defined alongthe sidewall surface 12 a on the cell side and along the bottom surface12 b of the trench 12 between the drain doping region 42 and the sourcedoping region 44.

According to the embodiment, preferably, PN junction depth 44 a of thesource doping region 44 on the digit side may be equal to the depth d ofthe trench 12. Compared to the prior art RCAT devices, the PN junctiondepth 42 a of the drain doping region 42 on the cell side may beshallower in order to maintain an adequate operation current level whenoperating the RCAT device 1. A contact (not shown) may be formed on thesource doping region 44 to couple to a digit line (not shown).

Structurally speaking, according to the embodiment and briefly referringto FIG. 7, the RCAT device 1 comprises a semiconductor substrate 10having thereon a trench 12 extending from a main surface 10 a of thesemiconductor substrate 10 to a predetermined depth d, a buried gateelectrode 16 a disposed at a lower portion of the trench 12, a gateoxide layer 14 between the buried gate electrode 16 a and thesemiconductor substrate 10, a drain doping region 42 on a first side(cell side) of the trench in the semiconductor substrate 10, and asource doping region 44 on a second side (digit side) of the trench. Thesource doping region 44 has a junction depth that is deeper than that ofthe drain doping region 42. An L-shaped channel 50 is defined along asidewall surface on the first side and along a bottom surface of thetrench 12 between the drain doping region 42 and the source dopingregion 44.

FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a RCAT device in accordance with anotherembodiment of the present invention. As shown in FIG. 8, after theformation of the buried gate electrode or word line 16 a, similar to theprocess step as depicted in FIG. 4, a planarization process such as aCMP process is carried out to remove excess dielectric layer 18 from themain surface 10 a of the semiconductor substrate 10. At this point, thepolished top surface of the dielectric layer 18 is substantially flushwith the main surface 10 a.

Subsequently, anion implantation process 142 is performed to implantdopants such as N type dopants into the main surface 10 a of thesemiconductor substrate 10, thereby forming a drain doping region 42 onthe cell side and a doping region 43 on the digit side. The junctiondepth of the drain doping region 42 is substantially equal to thejunction depth of the doping region 43.

As shown in FIG. 9, a pad layer 22 is then deposited in a blanketmanner. The pad layer 22 may be a silicon oxide layer. A hard mask layer24 such as a silicon nitride layer is then deposited on the pad layer22. A lithographic process and a dry etching process are performed tofrom a recess 30 in the semiconductor substrate 10 on the digit side. Atthis point, a portion of the dielectric layer 18 is revealed within therecess 30.

Using the hard mask layer 24 as an ion implant mask, an ion implantationprocess 144 is performed to implant dopants such as N type dopants intothe semiconductor substrate 10 on the digit side, thereby forming a RCATdevice la with asymmetric drain doping region 42 and source dopingregion 44.

Due to the recess 30 on the cell side of the RCAT device 1, the PNjunction depth 44 a of the source doping region 44 on the digit side canbe formed deeper than the PN junction depth 42 a of the drain dopingregion 42 on the cell side. A channel 50 is defined along the sidewallsurface 12 a on the cell side and along the bottom surface 12 b of thetrench 12 between the drain doping region 42 and the source dopingregion 44.

According to the embodiment, preferably, PN junction depth 44 a of thesource doping region 44 on the digit side may be equal to the depth d ofthe trench 12. Compared to the prior art RCAT devices, the PN junctiondepth 42 a of the drain doping region 42 on the cell side may beshallower in order to maintain an adequate operation current level whenoperating the RCAT device 1. A contact (not shown) may be formed on thesource doping region 44 to couple to a digit line (not shown).

As shown in FIG. 10, after the ion implantation process 144 is complete,the hard mask layer 24 may be removed.

FIGS. 11-13 are schematic, cross-sectional diagrams showing an exemplarymethod for fabricating a RCAT device in accordance with yet anotherembodiment of the present invention. As shown in FIG. 11, after theformation of the buried gate electrode or word line 16 a, similar to theprocess step as depicted in FIG. 4, a planarization process such as aCMP process is carried out to remove excess dielectric layer 18 from themain surface 10 a of the semiconductor substrate 10 . At this point, thepolished top surface of the dielectric layer 18 is substantially flushwith the main surface 10 a.

Likewise, an ion implantation process 142 is performed to implantdopants such as N type dopants into the main surface 10 a of thesemiconductor substrate 10, thereby forming a drain doping region 42 onthe cell side and a doping region 43 on the digit side. The junctiondepth of the drain doping region 42 is substantially equal to thejunction depth of the doping region 43.

As shown in FIG. 12, a pad layer 22 is then deposited in a blanketmanner. The pad layer 22 may be a silicon oxide layer. A hard mask layer(not shown in this figure) such as a silicon nitride layer is thendeposited on the pad layer 22. A lithographic process and a dry etchingprocess are performed to from a recess 30 in the semiconductor substrate10 on the digit side. At this point, a portion of the dielectric layer18 is revealed within the recess 30. Thereafter, the hard mask layer isstripped off, while leaving the pad layer 22 substantially intact.

As shown in FIG. 13, a doped polysilicon layer (not shown) is thendeposited on the semiconductor substrate 10 and fills the recess 30. Alithographic process and a dry etching process are performed to patternthe doped polysilicon layer into a contact element 60 situated directlyon the recess 30. A thermal process may be performed to drive thedopants from the contact element 60 into the portion of thesemiconductor substrate 10 that is in direct contact with the contactelement 60, thereby forming a source doping region 44.

The PN junction depth 44 a of the source doping region 44 on the digitside may be equal to the depth d of the trench 12. Compared to the priorart RCAT devices, the PN junction depth 42 a of the drain doping region42 on the cell side may be shallower in order to maintain an adequateoperation current level when operating the RCAT device 1 c. The contactelement 60 formed on the source doping region 44 may be coupled to adigit line (not shown).

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A recessed channel access transistor device, comprising: asemiconductor substrate having thereon a trench extending from a mainsurface of the semiconductor substrate to a predetermined depth; aburied gate electrode disposed at a lower portion of the trench; a gateoxide layer between the buried gate electrode and the semiconductorsubstrate; a drain doping region on a first side of the trench in thesemiconductor substrate; and a source doping region on a second side ofthe trench, wherein a top surface of the source doping region on thesecond side of the trench is lower than the main surface of thesemiconductor substrate, and wherein the source doping region has ajunction depth that is deeper than that of the drain doping region. 2.The recessed channel access transistor device according to claim 1further comprising a dielectric layer in the trench, wherein the buriedgate electrode is capped by the dielectric layer.
 3. The recessedchannel access transistor device according to claim 2 further comprisinga recess on the second side of the trench, wherein a portion of thedielectric layer is revealed within the recess.
 4. The recessed channelaccess transistor device according to claim 3 further comprising acontact element in the recess and in direct contact with the sourcedoping region.
 5. The recessed channel access transistor deviceaccording to claim 4 wherein the contact element is a doped polysilicon.6. The recessed channel access transistor device according to claim 1wherein the junction depth of the source doping region is substantiallyequal to the predetermined depth of the trench.
 7. The recessed channelaccess transistor device according to claim 1 further comprising anL-shaped channel along a sidewall surface on the first side and along abottom surface of the trench between the drain doping region and thesource doping region. 8-10. (canceled)